1. Field of the Invention
The present invention relates to a horizontal shift clock pulse selecting circuit for driving a color LCD panel used for driving an image signal of a color LCD panel, more specifically to a horizontal shift clock pulse selecting circuit for driving a color LCD panel, appropriate for driving with a skip period required in a PAL system.
2. Prior Art
With reference to pixel alignment in a color LCD panel, a color LCD panel of a delta alignment in which a pixel array is shifted by 0.5 pixel with respect to the adjacent array as shown in FIG. 2, and a color LCD panel of a stripe alignment in which pixels are vertically aligned in a straight line are known in the art. The present invention is appropriate for driving a color LCD panel of a delta alignment by a PAL system.
For driving a color LCD panel of a delta alignment, it is necessary to set a horizontal shift clock to provide a pulse for selecting a pixel, according to a pixel array. FIG. 3 shows odd number lines of horizontal shift clock CPHO1, CPHO2, CPHO3, and even number lines of horizontal shift clock CPHE1, CPHE2, CPHE3.
A rising of the odd number line horizontal shift clock CPHO1 and a rising of the odd number line horizontal shift clock CPHO2 are shifted by 1 pixel. A rising of the odd number line horizontal shift clock CPHO2 and a rising of the odd number line horizontal shift clock CPHO3 are shifted by 1 pixel. A rising of the odd number line horizontal shift clock CPHO3 and the rising of the next odd number line horizontal shift clock CPHO1 are shifted by 1 pixel.
Likewise, a rising of the even number line horizontal shift clock CPHE1 and a rising of the even number line horizontal shift clock CPHE2 are shifted by 1 pixel. A rising of the even number line horizontal shift clock CPHE2 and a rising of the even number line horizontal shift clock CPHE3 are shifted by 1 pixel. A rising of the even number line horizontal shift clock CPHE3 and the rising of the next even number line horizontal shift clock CPHE1 are shifted by 1 pixel.
Further, a rising of the odd number line horizontal shift clock CPHO1 and a rising of the even number line horizontal shift clock CPHE1 are shifted by 0.5 pixel.
Meanwhile, a display period of 1 field in a color LCD panel is different between an NTSC system and a PAL system. The display period of an NTSC system is 225 H, while that of a PAL system is 257 H. Therefore, for securing compatibility of a color LCD panel with the both systems, the display period of the PAL system is adjusted to that of the NTSC system by skipping horizontal scanning periods at a ratio of m (an arbitrary integer) horizontal scanning periods per n (an arbitrary integer, but m<n) horizontal scanning periods.
FIG. 6 shows a block diagram of a typical conventional horizontal shift clock pulse selecting circuit for driving a color LCD panel, and FIG. 7 shows timing charts of each section of the circuit. Operation of this circuit is described below referring to these drawings.
In FIG. 6, the reference numeral 1 shows a voltage controlled oscillator (VCO) in a phase lock loop (PLL).
Numeral 2 shows an odd number line horizontal shift clock generating circuit (ODD block). The odd number line horizontal shift clock generating circuit 2 generates the odd number line horizontal shift clocks CPHO1, CPHO2, CPHO3 shown in FIG. 3, based on an output signal from the voltage controlled oscillator (VCO).
Numeral 3 shows an even number line horizontal shift clock generator (EVEN block). The even number line horizontal shift clock generating circuit 3 generates the even number line horizontal shift clocks CPHE1, CPHE2, CPHE3 shown in FIG. 3, based on an output signal from the voltage controlled oscillator (VCO).
Numeral 4 shows a horizontal shift clock switching circuit consisting of 9 NAND circuits. The horizontal shift clock switching circuit 4 outputs horizontal shift clock outputs CPH1, CPH2, CPH3.
Numeral 5 shows an inverter.
Numeral 8 shows an ODD/EVEN selecting circuit constituted of the inverter 5. The ODD/EVEN selecting circuit 8 receives an input of a line identifying signal VCP33 by which to identify whether an odd number line or an even number line, and outputs NVCP33, which is an inverted signal of the line identifying signal VCP33.
Numeral 11 shows a color LCD panel (constituting a liquid crystal display unit) of a delta alignment.
Description on operation of the horizontal shift clock pulse selecting circuit for driving a color LCD panel is given hereunder.
The odd number line horizontal shift clocks CPHO1, CPHO2, CPHO3 generated by the odd number line horizontal shift clock generator 2 and the even number line horizontal shift clocks CPHE1, CPHE2, CPHE3 generated by the even number line horizontal shift clock generator 3 are alternately selected by the horizontal shift clock switching circuit 4 according to the line identifying signal VCP33 and the signal NVCP33 shown in FIG. 7, which is an inverted signal of VCP33, so that the horizontal shift clock switching circuit 4 outputs the horizontal shift clock outputs CPH1, CPH2, CPH3.
Accordingly, in this horizontal shift clock pulse selecting circuit for driving a color LCD panel, the odd number line horizontal shift clocks CPHO1, CPHO2, CPHO3 and the even number line horizontal shift clocks CPHE1, CPHE2, CPHE3 are alternately switched when inputting the horizontal shift clock outputs CPH1, CPH2, CPH3 to the color LCD panel 11.
As shown in FIG. 7, in a usual case of the PAL system the odd number line horizontal shift clocks CPHO1, CPHO2, CPHO3 are selected in the odd number line, and the even number line horizontal shift clocks CPHE1, CPHE2, CPHE3 are selected in the even number line, as the horizontal shift clock outputs CPH1, CPH2, CPH3. In other words, the odd number line horizontal shift clocks CPHO1, CPHO2, CPHO3 and the even number line horizontal shift clocks CPHE1, CPHE2, CPHE3 are alternately selected.
However, in a skip period, the line identifying signal VCP33 maintains the same state as the preceding line, as shown in FIG. 7. Therefore, the same odd number line or even number line horizontal shift clocks are selected as the horizontal shift clock outputs CPH1, CPH2, CPH3, to be input to the color LCD panel 11. Also, in a skip period, since the line does not advance though the horizontal shift clock outputs CPH1, CPH2, CPH3 are input to the color LCD panel 11, the image to be displayed is not affected. Consequently, the same display as the NTSC system becomes possible by the color LCS panel of the PAL system regardless of a phase of the horizontal shift clock in a skip period.
Meanwhile referring to FIG. 7, the reference code To shows an initialization time of the odd number line horizontal shift clock, and Te shows an initialization time of the even number line horizontal shift clock.
Also, for displaying through a color LCD panel of the NTSC system an image signal of the PAL system skipping a horizontal scanning line, a technique has been proposed for alleviating image quality degradation that consists in differentiating the horizontal scanning line to be skipped in the odd number field from that in the even number field, as well as differentiating by frame (For example, JP-A No. H5-37909, paragraphs 0013 to 0015, FIG. 1).
For driving a color LCD panel of a delta alignment, basically the odd number line horizontal shift clocks CPHO1, CPHO2, CPHO3 and the even number line horizontal shift clocks CPHE1, CPHE2, CPHE3 are alternately selected by the line as the horizontal shift clock outputs CPH1, CPH2, CPH3, and these outputs are input to the color LCD panel of a delta alignment 11.
At this stage, the horizontal shift clock outputs CPH1, CPH2, CPH3 affects an oscillation frequency of the voltage controlled oscillator 1, in a form of a digital switching noise. However, since the horizontal shift clock outputs CPH1, CPH2, CPH3 are switched at every line, the digital switching noise is leveled off and therefore influence thereof to an oscillation frequency of the voltage controlled oscillator 1 is minimal.
However, the horizontal shift clock pulse selecting circuit for driving a color LCD panel of the PAL system according to the conventional art has the following drawback because of skipping the scanning line. In a skip period in the PAL system the line identifying signal VCP33 is maintaining the same state as the preceding line and the horizontal shift clock outputs CPH1, CPH2, CPH3 are not switched. Accordingly, during m horizontal scanning periods out of n horizontal scanning periods, a horizontal shift clock of the same timing as that of the preceding line is output.
Specifically, in a skip period the switching of the horizontal shift clock is not executed alternately, therefore the horizontal shift clock outputs CPH1, CPH2, CPH3 are not leveled off. This means that the digital switching noise is not leveled off either. As a result, an oscillation frequency of the voltage controlled oscillator 1 in the phase lock loop is affected. For such reason a timing of horizontal shift clock outputs CPH1, CPH2, CPH3 are shifted from a desired timing. Consequently, when an image is displayed in the color LCD panel of a delta alignment, the image is shifted in a line next to the skipped line, therefore though a signal to display, for example, a straight line is input to the color LCD panel, the line is not displayed in a straight form.